Abstract
We report design optimization of new low-triggering dual-directional SCR (LTdSCR) ESD protection structures in BiCMOS. Design optimization techniques to adjust ESD triggering voltage (V t1 ), as well as its impacts on ESD holding voltage (V h ) and ESD protection capability, are discussed. Measurements show very low and adjustable V t1 , low leakage (I leak ), low noise figure (NF), low ESD-induced parasitic capacitance (C ESD ) and fast ESD triggering time (t 1 ). High ESD protection to Si ratio of ESDV∼7.49V/µm2 is achieved.
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