Design and Analysis of LIM Hybrid MTJ/CMOS Logic Gates

Abstract

Surge in the power dissipation due to increased leakage current has become one of the major concern in conventional CMOS VLSI design because of reduced transistor size, lower threshold voltage and lower supply voltage. To alleviate this, we have designed hybrid magnetic tunnel junction (MTJ)/CMOS circuits based on logic-in-memory (LIM) structure for various logic gates such as NAND/AND, NOR/OR and XNOR/XOR. This paper investigates the performance of hybrid gates and the results are compared with the conventional CMOS based gates in-terms of power, delay and device count. Hybrid gates designed in this paper are not only non-volatile in nature due to the use of MTJs but also they are found superior than the conventional CMOS circuits by dissipating less power and occupying smaller die area.