Design and analysis of an ultra-low-power double-tail latched comparator for biomedical applications

Abstract

This paper presents a new ultra-low power double-tail latched comparator suited for biomedical applications. The proposed comparator benefits from a positive feedback to achieve high resolution with low kickback noise. It is shown by time analysis and simulation that the delay time is significantly reduced compared to a conventional double-tail latched comparator. The presented circuit is designed and simulated in 0.18-μm CMOS technology. The post-layout simulation results show that the designed comparator consumes only 1.56 nW power, at 600 mV supply voltage and 100 kHz clock frequency. This amount is 54.35 % of power consumption of a conventional double-tail latched comparator with the same input referred offset of 7.5 mV. Furthermore, the proposed circuit provides a self-neutralization technique which results 8.8 % reduction of kick-back noise in comparison to the conventional latched comparator. The maximum clock frequency of this circuit is 200 MHz at 1 V supply voltage. The proposed circuit has a power-delay product of 0.0172 fJ at 100 kHz clock frequency. The proposed comparator is well designed to operate with supply voltages between 400 mV and 1 V.