Design of a Novel High Speed and Low kick back noise Dynamic Latch Comparator

Abstract

This article presents a new dynamic latch comparator suitable for fast applications with low kickback noise such as high-speed analog-to-digital converters (ADCS). This circuit reduces delay and the kick back noise. The maximum clock frequency for the suggestion comparator is 500MHZ at supply voltage of 1.8V while consuming 358μw. The technology is used for our proposed comparator is 0.18 μm CMOS technology.