A capacitive dynamic comparator with low kickback noise for pipelined ADC

Abstract

In this paper, a low kickback noise capacitive dynamic comparator is proposed. The low kickback noise is achieved by controlling additional MOSFETs in signal path to cancel voltage variation in the internal node of comparator. A neutralization technique is also implemented into the proposed design to further reduce the impact of kickback noise in the inputs of comparator. By adapting both techniques, the kickback noise of the proposed dynamic comparator is reduced 23 times smaller compared to that of conventional implementation at 500mV differential input voltage and 250MHz operating speed. The design is implemented in TSMC 0.18-μm CMOS technology process with 1.8V power supply and consumes 44.5μw power dissipation.