Abstract
A kickback noise capacitive dynamic comparator is presented. The low kickback noise is achieved by controlling additional MOSFETs in signal path to cancel voltage variation in the internal node of comparator. A neutralization technique is also implemented into the proposed design to further reduce the impact of kickback noise in the inputs of comparator. By adapting both techniques, the kickback noise of the proposed dynamic comparator is reduced 23 times smaller compared to that of conventional implementation at 500mV differential input voltage and 250MHz operating speed. The design is implemented in TSMC 0.18-μm CMOS technology process with 1.8V power supply and consumes 44.5μw power dissipation.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
