Abstract
Quantum-dot Cellular Automata (QCA) is one of the emerging computing paradigms. Its advantages such as smaller size, lower power consumption and faster speed are very attractive. QCA performs highly dense computing that could be realized in a variety of material systems. It is presently being investigated as an alternative to CMOS VLSI. In conventional digital systems the information is transferred from one place to another by means of electrical current, while as QCA cells transfer information by propagating a polarization state. This paper proposes a detailed design and simulation of a simple D flip-flop based sequential logic circuits like shift register, ring counter and modulo n counter circuits for quantum-dot cellular automata. The proposed designs are based on the D-type flip-flop (DFF) device. A QCA binary wire with four clocking zones can be used to implement a DFF. The aim is to maximize the circuit density and focus on a layout that is minimal in its use of cells.
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