Design and Analysis of 16nm GNRFET and CMOS Based Low Power 4kb SRAM Array Using 1-Bit 6T SRAM Cell

Abstract

With the evolution in the microelectronic applications like high speed processors, multimedia and in current electronic communication for artificial intelligent devices and IOT necessitates bigger SOC SRAM arrays for high performance with low power consumption and lesser space. Generally, CMOS based technology are most extensively utilized for designing of 6T SRAM cell. When the Nano scale technology is scaling down CMOS devices are usually confronting with leakage current and short channel impact. The constant scaling of CMOS technology restricts the performance of 6T SRAM cell in terms of leakage power. Leakage current is the biggest contributor in the power consumption of SRAM. So, the researchers have developed the optimistic technology using Graphene as a semi conducting channel. Graphene Nano Ribbon Field Effect Transistor (GNRFET) is a three terminal device similar to MOSFET, here the semiconducting channel is made with graphene. In this paper using 1-bit 6T SRAM cell, 4kb memory array is designed using CMOS and GNRFET technologies at 16nm technology with supply voltage of 1volt. Initially 4x4, 16x16, 32x32 SRAM arrays are designed in two technologies and the parameter such as read delay, write delay, power dissipation and average power are considered and the results are compared for the two technologies using HSPICE tool.