Design and analysis of 1-bit hybrid full adder cells for fast computation

Abstract

ABSTRACT This research article introduces a 1-bit Full Adder (FA) cell comprising 20 transistors, employing Gate Diffusion Input (GDI) and transmission gate logic. The FA cell is segmented into four modules: the first module encompasses an AND-OR module, followed by a module housing a Multiplexer (MUX) based on transmission gates for Carry Output generation. The remaining two modules are XOR gates dedicated to Sum Output generation. Simulation of the proposed design is conducted on the 45 nm technology node using Cadence Virtuoso and its GPDK 45 nm library. To validate the performance of the proposed design, it is compared against existing full adders. Performance parameters such as power consumption, delay and Power Delay Product (PDP) demonstrate superior performance across voltages ranging from 0.8 V–1.2 V.