Design analysis of GOS-HEFET on lower Subthreshold Swing SOI

Abstract

Due to various kind of Band-To-Band Tunneling (BTBT) operation, Heterojunction Tunnel Field Effect Transistors (HEFETs) are widely used in ultralow power applications. Anyhow, circuit complexity is a major issue in case of HEFET based memory development because of their uncomfortable size. Device scaling is a better way to eliminate such kind of issues for HEFET based memory development. Thus, development of Gate-oxide Overlapped Source-HEFET (GOS-HEFET) with lower Subthreshold Swing (SS) based Silicon on Insulator (SOI) is proposed to achieve perfect scaling in this work. Tunneling operation is done with the help of Si-based tunnel devices which are considerably lower than that of MOSFETs. Tunneling rate is enhanced by small bandgap material (Germanium (Ge)) in the source (S) while the ambipolar leakage is minimized by wide band gap material (Silicon (Si)) in the channel. Here, Ge is mainly utilized to dope the source region of P type transistor while Si is used to dope the drain (D) region of N type transistor. Moreover, the tunneling rate of BTBT is enhanced by the geometric alignment of the P and N type transistors with the gate oxide/semiconductor interface. Based on this procedure, five different kinds of SRAM (6 T, 7 T, 8 T, 9 T and 10 T) memory cells are designed. The proposed GOS-HEFET with lower SS on SOI design is implemented using SILVACO TCAD and TANNER CMOS technology. Then, power performance for different temperatures of the proposed method is compared with conventional HEFET based SRAM memory cells.