Dependence of normally-off GaAs JFET performance on device structure

Abstract

The relation between the performance of normally-off JFET's and the Si ion-implantation conditions used to form the channel layer was studied. Static and switching characteristics were investigated for JFET's with three kinds of channel layers; Si implanted at 130 keV to doses of 2,4, and 6 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> ions/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . While higher doses gave better static characteristics [I <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</inf> , g <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</inf> , and R <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</inf> ], higher capacitance degraded the switching characteristics. The optimum parameters were determined for the high-speed switching JFET. With 2-µm gate length, the highest switching speed was 80 ps and the lowest power-delay product was 0.9 fJ. An improved structure satisfying a high-conductance and low-capacitance requirement was successfully fabricated and showed excellent performance for high-speed and low-power logic circuits; the minimum propagation delay was 45 ps and the minimum power-delay product was 3.8 fJ with a delay time of 83 ps.