Demonstration of logic AND device using a split-gate pentacene field effect transistor

Abstract

We report on the fabrication and performance of pentacene-based split-gate field effect transistors (FETs) on doped Si/SiO 2 substrates. Several transistors with split gate structures were fabricated and demonstrated AND logic functionality. The transistor’s functionality was controlled by applying either 0 or − 10 V to each of the gate electrodes. When − 10 V was simultaneously applied to both gates, the transistor was conductive (ON), while any other combination of gate voltages rendered the transistor highly resistive (OFF). A significant advantage of this device is that AND logic devices with multiple inputs can be built using a single pentacene channel with multiple gates. The p-type carrier mobility of charge within the pentacene active layer of these transistors was about 10 − 5 cm 2/V-s. We attribute the low value of mobility primarily to the sharp contours of the pentacene film between the drain and the source contacts and to defects in the pentacene film. The average charge density was 1.4 × 10 12 holes/cm 2. Despite low mobility, the devices operated at lower drain-source ( V DS) and gate-source ( V GS) voltages as compared with previously reported pentacene based FETs.