Abstract
A high performance 4H-SiC vertical junction field effect transistor (VJFET) has been designed and fabricated using a self-aligned process which permits the formation of a highly vertical p/sup +/n junction gate and eliminates the need for epitaxial regrowth. Near 100% edge termination has been achieved, allowing the VJFETs to reach 392 V with a blocking layer of only 1.33 /spl mu/m doped to 2 /spl times/ 10/sup 16/ cm/sup -3/, reaching a record low R/sub ON/spl I.bar/SP/ of 1.4 m/spl Omega/ cm/sup 2/ at J/sub D/ up to 348 A/cm/sup 2/.
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