Abstract
The article analyses delay and power dissipation of a buffer-driven interconnect load in sub-threshold regime of operation. The investigations show that transistor operating in the sub-threshold region lead to an order of saving in power dissipation in contrast to normal strong inversion. A new compact mathematical model for the output voltages of a single complementary metal-oxide semiconductor (CMOS) buffer-driven global interconnect is developed. Global interconnect is modelled as an resistance-inductance-capacitance (RLC) load. Delay analysis of the global interconnect by this model is verified using simulation program with integrated circuit emphasis (SPICE) simulations. Good agreement between analytical and SPICE results is obtained. The analysis has been carried out for three technology nodes, viz. 130, 90 and 65nm.
Published Version
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