Degradation behavior of 0.5-μm p-channel metal–oxide–semiconductor transistors fabricated by means of x-ray and optical lithography

Abstract

Partially scaled p-channel metal–oxide–semiconductor surface channel transistors with effective channel lengths down to 0.20 μm have been successfully fabricated with x-ray and optical lithography at all four levels, respectively. The submicrometer feature sizes in the optical process were realized by the isotropic O2 plasma etch of the resist structures at the gate level. In order to determine the influence of x-ray radiation on the device parameters, a comparison of x-ray and optically processed transistors before and after hot-carrier stress was performed. The initial threshold voltage deviation before hot-carrier stress between both types of transistors was ΔVT=9 mV due to the hole trapping within the gate oxide of the x-ray exposed transistors. An absorbed dose of 2.5 Mrad within the 10-nm gate oxide was calculated by the simulation program xmas. The interface state density Dit measured by charge pumping reveals no difference and is in the order of 1.5×1010 1/eV cm2. After hot-carrier stress with a drain voltage VD=−6 V, a maximal VT shift of −18 mV was observed for 0.5-μm transistors. The ΔVT difference between optically and x-ray-processed 0.5-μm devices was 5 mV due to charge buildup of x-ray-induced neutral traps within the gate oxide. The tendency of higher negative VT shift of the x-ray-exposed wafers depends strongly on decreasing channel length and stress conditions. In the sub-half-micrometer range hot-carrier stress was performed with a reduced drain voltage VD=−3 V, which is a reasonable supply voltage, expected for the quarter-micrometer regime. Under these stress conditions the maximal VT shift was 7 mV for the x-ray transistors, which is within the technological process bandwidth.