Process-Induced Variability of SiC DMOSFET Short Circuit Capability

Abstract

Among compound semiconductors, Silicon Carbide (SiC) is useful especially in the high voltage, fast switching applications. Like with all technology areas, as SiC DMOSFET technology matures in terms of performance, questions of reliability and failure take on a more central role [1]. The short circuit (SC) capability addresses a key failure mechanism in these devices. The current and the lattice temperature of the device increase tremendously with the voltage stress leading to the device burning out. Among various reasons reported for this, the conducting paths created due to the melting of contacts (Aluminum) may be considered the most important factor [1]. In this work, we investigate the effect of possible process-induced variability on SC capability by 2-D simulation. Device and Simulation Setup A generic 1200 V vertical SiC DMOSFET structure, shown in Fig. 1, is simulated in a non-isothermal environment of the TCAD platform to study the short circuit capability of the device. Thus, we have used the thermodynamic model in addition to the usual drift-diffusion for electrons and holes. The parameters for bulk and interface mobility, its degradation with temperature, and thermal parameters such as thermal conductivity and specific heat capacity have been taken from the experimental literature. The acceptor type interface trap (Qa = 1.5x10 “cm at EG EE = 0.18 eV) and oxide fixed charge density 2x10 cm ~ are defined at SIC/SIO, for the simulation. The device is normally off type, and the important parameters are tabulated in Table 1. Results We consider the variability arising from two possible processes for self-aligned channel formation. The first, illustrated in Fig. 2.a, arises from the dry etch process used to form an oxide spacer which follows the p-well implant defined by the oxide hard mask. The spacer then acts as a hard mask during the n* source region implant so as to define the channel (additive). The distance between the two p-well, in this case, is fixed. Thus, channel length variability, in this case, is towards the n’-source side ('1'). The second, illustrated in Fig. 3.a, arises from a wet etch process to move back the oxide hard mask, which is used for the n*-source implant. The shortened oxide now constitutes a hard mask for the p-well implant, and thereby defines the channel (subtractive). The distance between the two n’ -source implants, in this case, is fixed. The channel length variability, in this case, is therefore from the JFET region side (‘2’). The total cell pitch remains constant in both cases. We consider both a decrease and an increase of channel length from each side. Fig. 2.6 shows the variability of type '1', while Fig. 3.6 shows the variability of type '2'. The effect of these variability types on the SC capability is different and depends on the effective channel length, which here ranges from 0.3 to 0.7 um. For type '1', the effective channel length increases and decreases with n’ -source, and most of the other device parameters are not affected as shown in Table 1. For type '2', the varied channel length is effectively changing the JFET dimensions. The combined effect is more pronounced which can be observed from the resulting SC curves. The SC capability of the device worsens with a decrease in channel length since that leads to higher currents. The results indicate that the additive method of fabrication is preferable for the SiC-based DMOSFET for reproducible SC performance. Acknowledgement This work was supported by the IIT Bombay-Ohio State Frontier Science and Engineering Research Center under “Towards the rugged SiC technology for electric transportation” project. Reference 1. Hema Lata Rao Maddi, Susanna Yu, Shengnan Zhu, Tian-shi Liu, Limeng Shi, Minseok Kang, Diang Xing, Suvendu Nayak, Marvin H. White, and Anant K. Agarwal, “The road to a robust and affordable SiC power MOSFET technology, “Energies, vol. 14, no. 24, pp. 8283, Dec 2021.