Defect structure and generation of interface states in MOS structures

Abstract

The correlation between the defect structure of the SiO 2 and the generation of interface traps upon avalanche injection of electrons and holes in MOS capacitor was investigated. Using samples with widely varying densities of intrinsic and H 2O-related trapping centers, and with different oxide thicknesses and gate electrodes it was established from experiments around room temperature that a one to one correlation between the densities of captured carriers and generated interface states exists as long as only a single type of carrier is involved. If simultaneously the second type of carrier is injected the picture becomes more complex. We confirm reports by other authors that at reduced temperatures (typically 77 K) two steps may be distinguished in the generation process, one of which is thermally activated. In this case the “yield” of interface states drops to values distinctly below one, even after warm up. In many cases the energy distribution of the states shows characteristic features: at E = E v + 0.45 eV for electron injection in samples with H 2O related traps, at E = E v + 0.75 eV for hole injection. Samples exhibiting these features always show the occurrence of slow states.