Abstract

Pseudorandom testing has been widely used in built-in self-testing of VLSI circuits. Although the defect level estimation for pseudorandom testing has been performed using sequential statical analysis, no closed form can be accomplished as complex combinatorial enumerations are involved. In this work, a Markov model is employed to describe the pseudorandom test behaviors. For the first time, a closed form of the defect level equation is derived by solving the differential equation extracted from the Markov model. The defect level equation clearly describes the relationships among defect level, fabrication yield, the number of all input combinations, circuit detectability (in terms of the worst single stuck-at fault), and pseudorandom test length. The Markov model is then extended to consider all single stuck-at faults, instead of only the worst single stuck-at fault. Results demonstrate that the defect level analysis for pseudorandom testing by only dealing with the worst single stuck-at fault is not adequate (In fact, the worst single stuck-at fault analysis is just a special case). A closed form of the defect level equation is successfully derived to incorporate all single stuck-at faults into consideration. Although our discussions are primarily based on the single struck-at fault model, it is not difficult to extend the results to other fault types.

Highlights

  • Defect level (DL) is an important indicator of test quality, and is defined as the percentage of a product, such as a chip, that is defective and is shipped for use after test

  • In [11], the DL of circuit testing is determined as a function of fault coverage and yield based on the following assumptions: (1) The chip has exactly n faults and m of them are tested; (2) The probability of a fault occurring is independent of whether any other fault has occurred or not; and

  • Fault coverage is available for deterministic test generation methods or random testing supported by fault simulation [2, 7]

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Summary

Introduction

Defect level (DL) is an important indicator of test quality, and is defined as the percentage of a product, such as a chip, that is defective and is shipped for use after test. Low DL can be achieved by either increasing the fabrication yield or enhancing the defect coverage of circuit testing. The DL of circuit testing is the probability of shipping defective products, and its value should be controlled to be as small as possible. If the number of defective products shipped for use among the total number of products shipped is known, the DL can be estimated using the following equation. In [11], the DL of circuit testing is determined as a function of fault coverage (the fraction of faults detected) and yield based on the following assumptions:. Where Y is the fabrication yield and T is the single stuck-at fault coverage. Equation (2) can be employed to find the DL of a testing method, if the yield and fault coverage are both known. Equation (2) shows that DL is exponentially related to fault coverage

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