DC‐20 GHz 5‐BIT CMOS digital step attenuator with low insertion loss and phase error

Abstract

AbstractThis article presents a 5‐bit broadband digital step attenuator with low insertion loss and phase error using a standard 0.13 μm CMOS process for the phased array antenna.The maximum attenuation of 31 dB with the LSB of 1 dB is achieved at DC‐20 GHz. The measured insertion loss of the reference state is <11 dB and the input and output return losses are <−10 dB at DC‐20 GHz. The root mean square (RMS) phase and amplitude errors are <2.5° and <0.7 dB, respectively. The current consumption is near zero with 1.2 V supply. The chip size is 1.04 × 0.48 mm2 including pads. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:762–764, 2013; View this article online at wileyonlinelibrary.com. DOI: 10.1002/mop.27448