Data-Aware Near Subthreshold 10 T SRAM Cell for Ultra-Low Power Application

Abstract

In the present era, high-performance computing is the most important feature for Artificial Intelligent and IoT applications. For edge devices, low power dissipation at high-performance computing capability is the highest priority constraint. Scale down the power supply voltage to reduce power dissipation is most effective. At lower supply voltage, data reliability is the major concern for the memory designers. In this paper, data-driven multi-threshold-based 10 T static random access memory (SRAM) cell with ultra-low leakage power and improved read/write stability at low supply voltage is proposed. With the utilization of differential data-dependent power supply mechanism and high threshold cross-coupled inverters, the energy efficiency of the proposed cell increased significantly. By the use of low threshold voltage transistors in the read buffer circuit, we observed a reduction in the read access time and enhanced the read reliability at low supply voltage. To perform read and write operations in the proposed memory cell, a single bitline is used. The leakage power of the proposed 10 T cell is compared with the conventional 6 T, differential data-aware power supply (D2AP) 8 T, and threshold voltage technique-based Vth_9T, (D2P) 11 T and from the obtained simulation results, it is concluded that the proposed cell has 50%, 50%, 48%, 46% less leakage power at 300 mV supply voltage. Read SNM achieved by proposed cell of 1.31X and 2.62X higher as compared to Vth_9T and data-dependent power supply (D2P) 11 T, respectively, at the same time, conventional 6 T and (D2AP) 8 T are unstable.