Design of SRAM cell using Voltage Lowering and Stacking Techniques for Low Power Applications

Abstract

The internet of things and intelligent wearable device are bringing new challenges to IC design, where the low static power dissipation and high stability is required for portable devices. In this paper, a design of static random access memory (SRAM) cell has been proposed with high stability and low static power dissipation. In this work a voltage lowering circuit has been used to enhance the write ability while read buffer has been used for enhance the read stability of SRAM cell. Moreover the stack transistor has also been used for reducing the leakage current which results in reduction of static power dissipation. This has been noticed that there is an enhancement in the WSNM of proposed design by 11%, 22%, 35%, 13.4% as compared to 6T [4], 7T [7], 8T [8], 10T [10] SRAM cells respectively, while reduction of 0.78% as compared to 9T [9]. It has also been observed that there is a reduction of 35%, 22%, 42.9%, 61% in the static power dissipation of proposed design as compared to 6T [4], 7T [7], 9T [9] and 10T [10] SRAM cells respectively. The proposed circuit is designed using 28 nm CMOS technology node at 1 V supply voltage while the cadence virtuoso tool has been used for verification of proposed design.