Abstract
Abstract The quaternary full adder accepts two quaternary inputs and a binary CARRY input and develops a two-quaternary-digit output word that is the base-four sum of the inputs. A current-mode CMOS circuit is presented that implements the quaternary threshold logic full adder function more area efficiently, with fewer current comparators and decoders (and hence transistors), than previously reported. It has been realized in standard polysilicon-gate CMOS technology.
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