Cu Pillar, RDL and Via Fill Challenges facing FOWLP

Abstract

The mobile market continues to push the limits of performance (electrical, power, thermal) and size. This paralleled with the challenges faced with continued wafer node reductions is driving the need for “More than Moore” through advanced vertical integration. One package form factor that has risen to meet these challenges and is being adopted by several end applications is the Fan Out Wafer Level Package (FO-WLP). This package is a modified version of standard Wafer Level Packages that provides a higher level of integration with an increased amount of I/Os. A variety of FOWLP packaging schemes are offered in the market (eWLB, InFO, SWIFT, etc.), each containing their own set of technical challenges (die first, die last, single RDL, multiple RDL layers, etc..). These challenges drive the need for optimized Cu, Sn, SnAg and Ni plating solutions for each package architecture, end application, die layout, plating tool, pillar construction, etc.. This presentation reviews the progression of Cu Pillars/Bumps, Redistribution Layers, and via fill requirements and how performance chemistry is being developed to meet these individualized needs.