Abstract
Application of the Object-Oriented Design of Reliable/Reconfigurable Architectures (OODRA) workbench to the performance simulation of a reconfigurable adaptive digital beamforming architecture is described in this paper. The performance effects due to chip/wafer partitioning and reconfiguration for fault tolerance and yield enhancement are presented. The experiments described illustrate use of the OODRA workbench in architectural-level performance evaluation of algorithm-specific reconfigurable architectures, particularly for signal processing applications.
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