Abstract
A method is presented that determines the coverage of shorts (bridging failures) in digital logic circuits by internal access test techniques. These are test techniques that provide observability of circuit nodes, such as CMOS power supply current monitoring (including IDDQ), CrossCheck, and voltage contrast. Only fault-free circuit simulation is used to obtain node states. Two versions of the algorithm are presented: a simple algorithm that is suitable for use with two-state logic (0 and 1), and a more general algorithm for four-state logic (0, 1, X, and Z). The result is a set of sets of nodes, where a list of all potential shorts that could exist in the circuit yet be undetected after testing is obtained easily from the power sets of these sets; unlike other approaches the full universe of potential shorts is not generated. Experiments show that short, randomly generated sequences of test vectors detect essentially all detectable shorts of multiplicity 2 for both combinational and sequential circuits.
Highlights
IntroductionA method is presented that determines the coverage of shorts (bridging failures) in digital logic circuits by internal access test techniques
A method is presented that determines the coverage of shorts in digital logic circuits by internal access test techniques
For the nonISCAS circuits, the sequences were chosen to be long enough to guarantee that each of the 100 sequences detected every detectable bridging failure; the value stated for the coverage is the best that any test vector sequence could achieve by measuring every node on every test vector
Summary
A method is presented that determines the coverage of shorts (bridging failures) in digital logic circuits by internal access test techniques. These are test techniques that provide observability of circuit nodes, such as CMOS power supply current monitoring (including IDDQ), CrossCheck, and voltage contrast. AND behavior (where a node in the 0 state would dominate a node in the 1 state) or wired-OR behavior (where a node in the 1 state would dominate a node in the 0 state) This is a valid assumption for lowresistance shorts in some circuit technologies and most published work so far is based on the "wired" behavior model for shorts. CMOS is currently the dominant digital circuit technology due to its low power, high speed, and high levels of integration, but the "wired" behavior model is not valid for CMOS bridging failures. The method of this paper, based as it is on "internal access" test techniques, is applicable to CMOS testing
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