Copper pillar bump technology progress overview

Abstract

Fine-pitch copper pillar bump (CPB) for flip chip assembly is expanding in package applications for mobile electronic devices due to the need for smaller form factor, thin thickness, and the demand for better performance and lower power consumption. This paper updates the recent technology progress in fine-pitch copper pillar bump design, structure, fabrication, and applications in flip chip and wafer level package assemblies. With the advent of chip scale packages (CSP) and wafer level packages (WLP), the need for very fine-pitch micro bumps became apparent when Intel first started to use copper bumps in its microprocessor packages. There are many variants in IP-protected copper pillar bump designs, including IBM's MPS-C2 (metal post solder chip connection), Advanpack (APS), and Intel coated copper bumps. Wafer level processing steps to fabricate electrodeposited CPB are discussed here. Experimental studies to verify the advanced, fine-pitch CPB design using customer-designed daisy chain test vehicle wafers are presented. Lastly, some examples of applications of the current CPB technology for use in flip chip packages and 3D IC package integration using TSV (through silicon via) are described. Recent reliability findings on the fine-pitch CPB are also included.