Contribution of Interface States and Oxide Traps to the Negative Bias Temperature Instability of High-$k$ pMOSFETs

Abstract

Negative bias temperature instability (NBTI) in MOSFETs with high-dielectric-constant (k) gate dielectrics has been investigated using a novel pulse NBTI measurement technique. This technique enabled the separation of the contribution of interface states (N it) from that of oxide traps (N ot) to NBTI behavior by varying the measurement time (t m) and the delay time (t R). The technique was demonstrated on devices fabricated with different postdeposition annealing (PDA) conditions. It was found that, regardless of the PDA condition, the N ot in high-k dielectric was more responsible for the NBTI behavior than the N it, but the contribution of N it to NBTI increased as the stress continued because the generation rate of N it was higher than that of N ot.