HCI and NBTI induced degradation in gate-all-around silicon nanowire transistors

Abstract

The silicon nanowire transistor (SNWT) with gate-all-around (GAA) structure can be considered as one of the potential candidates for ultimate scaling due to its superior gate control capability and improved carrier transportation property. In this paper, hot carrier injection (HCI) and negative bias temperature instability (NBTI) behavior of n-type and p-type SNWTs with top-down approach is discussed. In addition to initial fast degradation and quick saturation of NBTI stress behavior, non-negligible impacts of electron traps on the stress/recovery characteristics in p-SNWTs with metal gate is found and characterized with a kind of combined Ig–Id RTN technique. The NBTI behavior is modeled taking account of the impacts from unique structural nature of GAA SNWTs. NBTI induced performance degradation of the typical nanowire-based circuits is estimated based on the proposed model. In addition, stochastic degradation induced by single/few trap in the thin-body SNWTs is observed and analyzed.