Abstract
A novel approach to achieve concurrent error detection in finite-field multiplication over GF(2 m ) that uses multiple-bit interlaced parity codes is presented. These codes are implemented as a generic parity checker, which means they can be used with any multiplier architecture. Relative to the number of parity bits used, much improved delay and error-detection performance are achieved compared to previously reported results, yet for the examples considered the area overhead did not exceed 12%. The proposed work is particularly important for cryptography implementations employing GF(2 m ) multipliers and requiring reliability and protection against adversarial attacks that use fault induction.
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