A Scalable Bit-Parallel Word-Serial Multiplier with Fault Detection on GF(2^m)

Abstract

In this paper, a scalable bit-parallel word-serial (BPWS) finite field multiplier with fault detection capability on binary extension fields is proposed for elliptic curve cryptography (ECC). The proposed multiplier aims at low-complexity implementation meanwhile obtaining high fault detection performance. Firstly, to reduce area cost, we use a 9-bit register for the configuration of modular reduction so the multiplier can accommodate all five finite field recommended by National Institute of Standard and Technology (NIST). Then, a parity-based concurrent error detection (CED) approach is employed to increase the reliability. Finally, we analyze the capability and overheads of the CED scheme based on ASIC simulation. We show that the employed 1-bit parity detection approach results in 100% stuck-at fault detection c with small time and area overheads, while the best existing one use 4-bit parity detection to achieve 100% fault detection.