Concurrency Preserving Partitioning Algorithm for
Parallel Logic Simulation

Jack Jean,Hong K. Kim

doi:10.1155/1999/18373

Abstract

A partitioning algorithm for parallel discrete event gate-level logic simulations is proposed in this paper. Unlike most other partitioning algorithms, the proposed algorithm preserves computation concurrency by assigning to processors circuit gates that can be evaluated at about the same time. As a result, the improved concurrency preserving partitioning (iCPP) algorithm can provide better load balancing throughout the period of a parallel simulation. This is especially important when the algorithm is used together with a Time Warp simulation where a high degree of concurrency can lead to fewer rollbacks and better performance. The algorithm consists of three phases and three conflicting goals can be separately considered so to reduce computational complexity.To evaluate the quality of partitioning algorithms in terms of preserving concurrency, a concurrency metric that requires neither sequential nor parallel simulation is proposed. A levelization technique is used in computing the metric so to determine gates which can be evaluated at about the same time. A parallel gate-level logic simulator is implemented on an INTEL Paragon and an IBM SP2 to evaluate the performance of the iCPP algorithm. The results are compared with several other partitioning algorithms to show that the iCPP algorithm does preserve concurrency pretty well and reasonable speedup may be achieved with the algorithm.

Highlights

Logic simulation is a primary tool for validation and analysis of digital circuits
As in many other parallel simulations, a good partitioning algorithm is a key to achieve good performance in parallel logic simulation, especially since the event granularity is relatively small compared to other types of simulations
Since dynamic partitioning involves a lot of communication overhead [16], static partitioning is considered in this paper

Summary

Introduction

Logic simulation is a primary tool for validation and analysis of digital circuits. To reduce the simulation time of large circuits, parallel logic simulation has attracted considerable interest in recent years [1]. As in many other parallel simulations, a good partitioning algorithm is a key to achieve good performance in parallel logic simulation, especially since the event granularity is relatively small compared to other types of simulations. JEAN be classified into two categories: static and dynamic. Static partitioning is performed prior to the execution of the simulation and the resulting partition is fixed during the simulation. A dynamic partitioning scheme attempts to keep system resources busy by migrating computation processes during the simulation. Since dynamic partitioning involves a lot of communication overhead [16], static partitioning is considered in this paper

Methods

Results

Conclusion