Abstract
Interconnect imperfections have become an important issue in modern nanometer technologies. Some of them cause Small Delay Defects (SDDs) which are difficult to detect. Those SDDs not detected during testing may pose a reliability problem. Furthermore, nanometer issues (e.g. process variations, spatial correlations) represent important challenges for traditional delay test methods. In this paper, a methodology to compute the Detection Probability (DP) of resistive open and bridge defects using a statistical timing framework that takes into account process variations and other nanometer issues is proposed. The DP gives the sensitivity of the circuit performance to a given resistance range of the defect. The efficiency issue when analyzing large circuits is alleviated using stratified sampling techniques to reduce the space of possible analyzed defect locations This methodology is applied to some ISCAS benchmark circuits. The obtained results show the feasibility of the proposed methodology. Measures can be taken for those circuits presenting non-acceptable DP in order to improve the test quality.
Published Version
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