Computer-Aided Logic Synthesis for VLSI Chips

Abstract

Logic design in designing computers generally means the design of a logic network, with prespecified types of logic gates, that realizes a given logic function. This chapter provides an overview of the research on automated logic synthesis, the design of minimal logic networks by integer programming, the transduction method for the design of NOR logic networks, the logic design of MOS networks, and SYLON—the new Logic-Synthesis system. Minimal networks do not necessarily lead to the most compact layout on a chip, but minimal or near-minimal networks generally would lead to the most compact layouts. Because of the progress of the VLSI technology, a single chip can be packed with an enormous number of transistors. The transduction method is based on the following: design of an initial network, reduction of a network, transformation of a network, and repetition of reduction and transformation. The significance of the transduction method is the introduction of the basic concept whereby local and/or global transformation and reduction were repeatedly applied to initial networks at a time when initial networks with simple transformations based on certain connection patterns were considered to be the final result of the logic design. Future computers will consist of a far larger number of logic gates than present ones. Faced only recently with the formidable task of designing networks with such a large number of logic gates, the computer industry has no choice but to use automated logic synthesis. This is just the beginning of extensive use of automated logic synthesis, and will need many years to improve it in numerous aspects, such as computational efficiency, capability of handling logic networks of ever-increasing size, quality of designed networks, and types of electronic circuits.