Comprehensive study of the impact of TSV induced thermo-mechanical stress on 3D IC device performance

Abstract

Impact caused by Through-Silicon Via (TSV) induced thermo-mechanical stress on device performance has been a concern for three-dimensional (3D) integrated circuit (IC) integration because of the close proximity of TSVs to semiconductor devices. From the literatures, there are conflicting reports between theory, simulated and experimental results. For realistic and reasonably accurate predictions, the stress build-up by taking the full CMOS process flow into consideration is simulated. We investigated various key factors such as the orientation of TSV to device, device channel length and different CMOS technologies on the impact of TSV induced thermo-mechanical stress on device performance. Results exhibit that TSV induced stress impacts more on long channel nMOSFETs typically used in analog applications than that on digital devices of minimum channel length for the same CMOS technology. This is mainly due to the decrease in the impact of tensile stress liner in the long channel nMOSFET. In addition, the impact of TSV induced stress on nMOSFET devices of the same channel length of 180 nm is found to be larger for 130 nm technology than 28 nm and 65 nm technologies, which resolves conflicts in past reports.