Abstract
In this paper, we propose a comprehensive analysis of ultrathin oxide reliability that includes the validation of the power law model (TBD∼V-n), area scaling (TBD∼A-1/β), and process optimization. We show that the power law exponent n (=38) of a pFET is less than that of a nFET (n=48). Then a proper area range for β determination and process optimization for n improvement are pointed out, especially for pFETs. A novel explanation is discussed of ultrathin oxide pFET degradation behavior with lower decoupled plasma nitridation (DPN) pressure or higher substrate bias stress (Vbs>0 V) that lowers the exponent in power-law fitting. This phenomenon shortens the lifetime predicted for ultrathin oxide pFETs. From the view of reliability projections, a new failure criterion is suggested with and further extended to 65 nm technology and to higher operating voltage applications.
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