Ultra thin oxide reliability: effects of gate doping concentration and poly-Si/SiO/sub 2/ interface stress relaxation

Abstract

Dielectric breakdown of ultra thin (thickness <100 /spl Aring/) oxide is a major concern for ULSI circuit failure. Recent studies have found that the condition of the polysilicon gate can play an important role in the reliability of thin gate oxides. In this paper, the impact of gate doping concentration on the ultra-thin gate oxide reliability was investigated for oxides of thickness ranging from 45 /spl Aring/ to 85 /spl Aring/. Different gate deposition conditions (poly or amorphous), different dopant species (phosphorus or arsenic) and wide range of doping concentration (from 1.0/spl times/10/sup 19/ to 6.7/spl times/10/sup 20/ cm/sup -3/) were used. It was found that charge-to-breakdown under substrate injection stress (Q/sub BD/(+V/sub g/)) shows a notable improvement as the doping concentration reaches some threshold value, while Q/sub BD/(-V/sub g/) is almost independent of doping concentration. The difference of Q/sub BD/(+V/sub g/) between high and low doping concentrations becomes more significant as the oxide is scaled down. These observations coupled with material analysis suggest that dopant-related stress/strain at the gate/oxide interface may play a critical role in the oxide breakdown behavior.