Abstract
This paper investigates trap-induced degradation in nmosfets with HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate dielectric by three-dimensional Kinetic Monte Carlo method. Multiple microscopic mechanisms including trapping/detrapping, traps coupling, and trap generation/recombination are considered in simulation. The impacts of interfacial layer (IL) SiOx on positive bias temperature instability (PBTI) and trap-assisted tunneling (TAT) are comprehensively investigated. PBTI characteristics show the variations of power laws with time, and power laws are greatly affected by stress condition, trap density, and dielectric thickness. Therefore, impressionable power laws make much complexion in lifetime prediction. Meanwhile, it is found that IL markedly reduces PBTI effects. Significantly, TAT currents of fresh devices increase with IL thickening in the same effective oxide thickness (EOT), whereas TAT currents after stress decrease with IL thickening in a specific range. It can be concluded that the IL in the proper range of thickness can effectively suppress PBTI and TAT currents.
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