PBTI in HKMG nMOS Transistors— Effect of Width, Layout, and Other Technological Parameters

Abstract

This paper discusses in detail the effects of transistor width, layout, and technological parameters like gate dielectric and Lanthanum capping layer thickness on positive bias temperature instability (PBTI) of nMOS transistors fabricated using 28-nm gate-first High- ${K}$ metal gate CMOS technology. It is shown that the PBTI reduces with decrease in width ( ${W}$ ), increase in capping layer thickness and decrease in high- ${K}$ dielectric thickness. The physical mechanisms responsible for these dependencies are investigated and attributed to the modulation of preexisting traps in the high- ${K}$ dielectric and the modulation of electron injection into these traps. It is also shown that the PBTI of the devices could be improved by dividing a single active into multiple actives, by increasing active-to-active spacing and gate pitch.