Comprehensive BEOL control using scatterometry and APC

Abstract

Copper interconnects have been adopted in advanced semiconductor manufacturing due to benefits of reduced RC delay, cross talk and power consumption. With each technology node, interconnects reduce in size resulting in increased line resistivity, a critical metric in determining the device performance. Reactive Ion Etching (RIE) and Copper Chemical Mechanical Polishing (Cu CMP) are two of the key back end of the line (BEOL) processes that affect the interconnect performance. Due to variations from incoming processes and the inherent variability induced by these processes, dielectric trench depth and resulting copper line height variations that can potentially result from these processes have direct impact to RC delay. Traditional inline metrology methods used are time consuming and do not provide the needed wafer level metrics. In addition, measurement of remaining dielectric thickness on solid pads is not a good representative of the actual device structures and has been inaccurate for process due to dishing of the copper pads. Efficient control of BEOL processes requires measurement of metal line thickness and other critical profile parameters from which resistance can be extracted. In order to relate BEOL process steps and understand their interactions, it is necessary to have a directly comparable measurement methodology on a similar measurement structure. Over the past several years, scatterometry has been proven as the only metrology method to provide the full profile information of the Cu lines. Scatterometry is a diffraction based optical measurement technique using Rigorous Coupled Wave Analysis (RCWA), where light diffracted from a periodic structure is used to characterize the details of profile. Unique algorithms, such as Holistic Metrology can be used to make the scatterometry development process faster. In this paper, we will present how scatterometry can be used to measure copper line height on 3D structures and how feed forward from RIE can be applied for control of Cu CMP process for 20nm technology node. The importance of incoming trench depth variations is demonstrated for CMP polish time control in order to stabilize the copper line height. Validation data is presented for different scatterometry models including accuracy, repeatability and DoE tracking. Electrical resistance is shown to correlate to the copper trench profile measured by scatterometry. The paper will demonstrate the capability for reducing copper line height variation and the correlation of the reducing trench height variation to improved stabilization of electrical resistance.