Component Level Reliability Evaluation of Low Cost 6-Sided Die Protection versus Wafer Level Chip Scale Packaging with 350um Ball Pitch

Abstract

Fan-In Wafer Level Chip Scale Packaging (WLCSP) continues to be the lowest package cost and smallest package size in comparison to Fan-Out Wafer Level Packaging (FOWLP) or Panel Level Packaging (PLP) for the past 5 years. However, Fan-In WLCSP faces inherent limitations due to its limited space for re-routing I/Os, limitations on multiple redistribution layers that would subsequently affect wafer warpage and increased cost per redistribution layer. In majority of cases, a WLCSP package will require underfill for the board assembly process to ensure no issues with solder joint reliability or other defects due to final sawn die handling for board assembly.In comparison to WLCSP, the cost for a 6-sided die protection is inherently higher due to added processes for reconstitution post die prep and panel backgrind prior to thin film processes. However, Fan-Out can have a number of interconnects with standard ball pitches independent of die size with options for multi-die assembly and 3D interconnects. The key is to lower the cost of Fan-Out packaging while maintaining its superior package reliability over traditional WLCSP packages.This paper will describe the differences between a WLCSP package and 6-sided die protection Fan-Out package of a 7mm x 7mm, 0.35mm ball pitch test vehicle. We will review the Component Level Reliability (CLR) results for a 4 mask layer WLCSP (2P2M) versus 4 mask (2P2M) and 3 mask (2P1M, 1P2M) layer 6-sided die protection Fan-Out package with SAC405 solder ball. Package cross sections will be presented for each CLR read points, BLR simulation comparing WLCSP vs Fan-Out with reduced mask layer counts will be shared and estimate cost analysis for a given package will be presented as tradeoff for utilizing 6sided die protection for Fan-Out versus WLCSP.