Complete data and address generation for memory testing using modified LFSR structures

Abstract

March-based algorithms are important in testing of memory cores especially in Memory BIST architectures as it provides good fault coverage. For Memory testing, we need test vectors and addressing sequences. Conventional methods use Linear Feedback Shift Register (LFSR) for generating test vectors and counter circuits for the address generation. With the modified LFSR structure we can replace the need for two circuits by a single circuit. This paper focuses on developing two structures; a Complete Linear Feedback Shift Register (CLFSR) and a Configurable CLFSR. Both are configured by modifying LFSR circuit. CLFSR can be used for the generation of both test vectors and addressing sequences. Hence it enables to replace LFSR and Counter circuits in a conventional Built-in Self-Test architecture by a single circuit. This reduces the complexity and hardware requirement of the architecture. It has been found that, two addressing orders are required to perform the memory test using March test algorithms. The proposed Configurable CLFSR provides the two addressing sequences for the March Test algorithms in a simple way with less hardware. The effectiveness of this architecture is evaluated by implementing it in March C-algorithm. Functional verifications and Simulations are done using Verilog HDL in Xilinx ISE 14.2.