Abstract
This paper proposes the pseudo random number generator (PRNG) circuit with three linear feedback shift register (LFSR) design, which generates cryptographically more secured pseudo random number than a conventional LFSR system. In this configuration, the three different LFSRs (4, 5 and 7-bit) are triggered with same positive edged clock pulse. A 1-bit comparator is employed as intermediate stage to compare the outputs of 4 and 5-bit LFSRs. The subsequent output of the 1-bit comparator has been XORed with the feedback XOR output of the 7-bit LFSR. This introduces the desired inequality in recurrence relations of the three LFSRs used to enhance the overall linear complexity of the proposed LFSR circuit. The power consumption of the proposed compact LFSR circuit is less than the conventional 16-bit LFSR.
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