Competitive Performance Analysis of 3T DRAM Cell Using Power Reduction Techniques

Abstract

The objective of this paper is to compare the power consumption, leakage voltage, leakage current and leakage power of 3-T DRAM while maintaining the competitive performance .The MTCOS and SVL technique is used in 3T DRAM to compare the performance. Multi-threshold CMOS(MTCMOS) is a CMOS chip which has a Transistor with multiple threshold voltage and SVL is a technique which used to reduce leakage during both the active and stand-by mode. DRAM was first invented by Dr. Robert Dennard in the year 1966. It is used in many advanced processor for chip instruction and data memory. It majorly contributes in power dissipation in off-state leakage current. In personal computers it is used as the main memory, workstations etc. The basic advantage of using DRAM is its simplicity in its structure. Keyword- DRAM; FinFET; CMOS; Leakage power; Leakage current; Frequency; Access time; MTCMOS; SVL; USVL; LSVL