Comparison of various ATPG Techniques to Determine Optimal BIST

Abstract

This paper thoroughly analyses all major ATPG (Automatic Test Pattern Generator) techniques to predict which of these would be optimal for a specific bit sized CUT (Circuit Under Test) when incorporated with BIST (Built-in-Self-Test). ISCAS benchmark circuits (74XX series) were used as CUT's and LFSR (Linear Feedback Shift Register), BS-CSFR (Bit-Swapping Complete Feedback Shift Register) and CA (Cellular Automata) based prominent ATPG techniques were used as vector generators. To make the predictions stronger, simulation was carried out on two benchmark circuits by Texas Instruments IC number 74181 and 74283. LFSR is the fundamental pattern generator and will serve as the base of comparison. BS-CFSR has shown promising transition density reduction without affecting the pseudo-randomness in the patterns whereby reducing the power considerably. CA avoids long feedback loops and communicates with neighbour cells only, which in turn helps to generate more random patterns and have better fault coverage. Xilinx ISE 14.7 and Cadence Encounter RTL Compiler RC 14.10 for coding in Verilog and implementation were used for timing responses, power consumption, delay and area of each implementation at 45 nm technology node.