Implementation of Low-Power BIST Using Bit Swapping Complete Feedback Shift Register (BSCFSR)

Abstract

Design for Testability (DFT) has been a major concern for today’s VLSI engineers. A poorly designed DFT would result in losses for manufacturers with a considerable rework for the designers. BIST (Built-in Self-Test)—nne of the promising DFT techniques is rapidly modifying with the advances in technology as devices shrink. Because of the growing complexities of the hardware, the trend has shifted to include BISTs in high performance circuitry for offline as well as online testing. Work done here involves testing a Circuit Under Test (CUT) with built-in response analyzer and vector generator with a monitor to control all the activities. Use of low transition vector generators here Bit-Swapping Complete Feedback Shift Register (BS-CFSR), power has been reduced considerably when compared to classical Linear Feedback Shift Register (LFSR) techniques. This presents the process of design implementation for a complete BIST working on both normal operation mode as well as test mode for any 4 bits’ circuitry. Xilinx ISE 14.7 for coding in Verilog and implementation with Cadence’s Encounter(R) RTL Compiler RC 14.10 was 70used for timing responses, with power consumption calculated at different technology nodes. In IoT applications, reliability of electronic devices plays a crucial role. A faulty design cannot support reliable components and sensors. Therefore BS-CFSR will be best BIST structure to test and rectify any fault occurrence at system level.