Comparison of the thermal performance of wire bonded and flip chip CSP's

Abstract

The trends in the electronics packaging industry towards miniaturization have resulted in increased I/O over a smaller printed circuit board area. Simultaneously the power output of chips has steadily increased resulting in ever increasing watt densities. These two trends of smaller packaging and higher power have driven the packaging industry towards area array packages such as Ball Grid Array (BGA), Chip Scale Packages (CSP) and flip chips. Though flip chips are not commonly used in a Chip-on-Board format (issues with rework of underfill), it is becoming the technology of choice for 1/sup st/ level packaging. The reason for this is that flip chip designs provide higher I/O density, better electrical performance, reduced cost and improved thermal performance. The trend towards increasing chip power densities makes this last advantage of particular interest to board designers and thermal engineers. The focus of this paper is to compare the thermal performance of wire bonded and flip chip CSP's. Compact models have been developed for both configurations and will be discussed in detail. This paper will also compare the commonly used two-resistor compact model to detailed chip model.