Optimization of interconnections structure in the fine pitch FCCSP for low-k dielectric reliability

Abstract

There are many challenges to overcome including cost-effective manufacturing and assembly as well as the low-k reliability in the flip-chip chip scale package(FCCSP). In particular, a technology to achieve reliability of a low-k dielectric is the key to robust interconnection design in FCCSP. The main purpose of the present study is to design optimum interconnection structure in the fine pitch FCCSP for the low-k dielectric. Finite element analysis(FEA) and the Taguchi method are used with fine pitch of 90μm and 100μm under thermo-mechanical loading in a FCCSP. The normal and shear stress of the interconnection are calculated to predict reliability of a low-k dielectric with various conditions (interconnection structures and PCB structure). Normal and shear stress of low-k as well as FCCSP warpage and displacement difference between a chip and a substrate are analyzed to understand a correlation the low-k reliability and the thermo-mechanical deformation of FCCSP. Four interconnection design factors(structures, diameter, height and solder volume) are used with three levels in the Taguchi method. The normal and shear stress of a low-k dielectric is low as FCCSP warpage and displacement difference between a chip and a substrate decreases, respectively. In the Taguchi method, a comparison among interconnections structures(a copper pillar-solder(Sn0.7Cu)-copper pillar, a copper pillar-solder(Sn0.7Cu), a solder(Sn0.7Cu)-copper pillar) reveals that low-k stress can be low with low solder volume. Specially, a solder to a chip side was more advantage rather than to a substrate side for low stress of a low-k dielectric. The normal stress of a low-k dielectric could be reduced with interconnection height of 60μm and diameter of 60μm. However, shear stress is low with diameter of 40μm. Finally, the plastic strain energy density(PSED) of the solder joints was calculated as PCB layer structures. From this result, package reliability may be overestimated if the package is modeled with one layer of PCB. Therefore, it is suggested that multiple layers of PCB be modeled in FEA to improve the accuracy of thermal package deformation. These studies will be presented in details including FEA and experimental tests. In the near future, to reduce stress in the low-k dielectric it is recommended that the optimized copper interconnection volume be determined considering all materials in a FCCSP for better package reliability. The reliability of a Low-k dielectric can be predicted without time delay by this study results at package level.