Flip chip chip scale packaging: transferring the flip chip density requirements from the motherboard to the chip carrier

Abstract

Area array packages allow the user to integrate greater functionality into smaller form factor products. These products must use low cost, compact, lightweight and highly reliable packaging solutions or migrate directly to flip chip attach. Many companies are performing flip chip attach directly to motherboards to achieve increased functionality and performance, but this increases the complexity of the substrate technology needed for this type of assembly. Another way to improve motherboard area usage and increase overall silicon density over conventional fine pitch QFP and ball grid array (BGA) technologies is to use fine pitch BGAs (FBGA) and chip scale packages (CSPs). The Advanced Interconnection Systems Laboratory is developing a laminate based flip-chip chip scale package (FC-CSP) technology, JACS-Pak/sup TM/ (just about chip size package), for ICs with low to moderate I/O pin counts (<150). As these packages must be cost competitive with conventional SMT packages, inexpensive high density substrate technologies must be used. The JACS-Pak/sup TM/ package family currently supports 0.5 mm, 0.65 mm and 0.8 mm pitch applications. These packages are fully compatible with SMT processing. This paper focuses on the requirements of the chip carriers to handle flip chip attach and the impact of the chip carrier on the assembly process. Recommendations with respect to the motherboard PCB technology required to route these FBGAs and CSPs are given. As higher I/O packages are used, users must migrate to HDI PCB technology to fully utilize the capability of these packages.