Abstract
Abstract Large area silicon pixel trackers are currently under development for the High Luminosity upgrade of the LHC detectors. They are also foreseen for the detectors proposed for the future high energy Compact Linear Collider CLIC. For the CLIC tracker a single hit resolution of 7 μ m, a timing resolution of a few nanoseconds and a material budget of 1–2 % of radiation length per detection layer are required. Integrated CMOS technologies are promising candidates to reduce the cost, facilitate the production and to achieve a low material budget. CMOS sensors with a small size of the collection electrode benefit from a small sensor capacitance, resulting in a large signal to noise ratio and a low power consumption. The Investigator is a test-chip developed for the ALICE Inner Tracking System upgrade, implemented in a 180 nm CMOS process with a small collection electrode on a high resistivity epitaxial layer. The Investigator has been produced in different process variants: the standard process and a modified process, where an additional N-layer has been inserted to obtain full lateral depletion. This paper presents a comparison of test-beam results for both process variants, focuses on spatial and timing resolution as well as efficiency measurements.
Highlights
The Compact Linear Collider, CLIC, is a future option for a linear electron-positron collider in the post-LHC era at CERN [1,2,3,4]
A large area silicon tracker with a surface of approximately 140 m2 is proposed for the CLIC detector
Due to the small junction and the limited bias voltage the depletion in the standard process is restricted to regions around the collection electrode, while a full lateral depletion can be achieved for the modified process [9]
Summary
The Compact Linear Collider, CLIC, is a future option for a linear electron-positron collider in the post-LHC era at CERN [1,2,3,4]. A hit time resolution of a few nanoseconds is required, to suppress outof-time background from beam–beam interactions [6] To address these requirements, a large area silicon tracker with a surface of approximately 140 m2 is proposed for the CLIC detector. The Investigator pixel layout has been designed to minimise the sensor capacitance to a few fF [8] In this way, a low analogue power consumption, a low noise and a large signal to noise ratio can be achieved. The original process used for the ALPIDE chip has been modified to achieve full lateral depletion of the sensor volume [9]. Both process variants have been studied and a comparison of the results is presented in this paper. This paper focuses on the comparison of test-beam results for the standard and modified process
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