Simulations of CMOS pixel sensors with a small collection electrode, improved for a faster charge collection and increased radiation tolerance

M Munker,M Benoit,P Riedler,D Dannheim,T Leitner,T Kugathasan,A Fenigstein,H Pernegger,W Snoeys

doi:10.1088/1748-0221/14/05/c05013

Abstract

CMOS pixel sensors with a small collection electrode combine the advantages of a small sensor capacitance with the advantages of a fully monolithic design. The small sensor capacitance results in a large ratio of signal-to-noise and a low analogue power consumption, while the monolithic design reduces the material budget, cost and production effort. However, the low electric field in the pixel corners of such sensors results in an increased charge collection time, that makes a fully efficient operation after irradiation and a timing resolution in the order of nanoseconds challenging for pixel sizes larger than approximately forty micrometers. This paper presents the development of concepts of CMOS sensors with a small collection electrode to overcome these limitations, using three-dimensional Technology Computer Aided Design simulations. The studied design uses a 0.18 μm process implemented on a high-resistivity epitaxial layer.

Highlights

This paper presents the development of concepts of CMOS sensors with a small collection electrode to overcome these limitations, using three-dimensional Technology Computer Aided Design simulations
In this standard process, it is difficult to make the depletion layer extend from the junction around the small collection electrode laterally in the epitaxial layer between deep p-well and substrate, especially if the readout circuitry occupies a large fraction of the pixel area
By combining the advantages of a small sensor capacitance and a fully monolithic technology, CMOS pixel sensors with a small collection electrode address the requirements of future experiments

Summary

Standard and modified process

A 0.18 μm CMOS imaging process with a small collection electrode has been studied, as sketched in figure 1. All implants are placed on a high resistivity epitaxial layer that is grown on a low resistivity backside substrate to maximise the depleted region in the sensor. In this standard process (see left side of figure 1), it is difficult to make the depletion layer extend from the junction around the small collection electrode laterally in the epitaxial layer between deep p-well and substrate, especially if the readout circuitry occupies a large fraction of the pixel area. The concept of moving the junction from a small area around the collection electrode to a larger area deeper in the sensor has been pursued in developments to combine full depletion with a small collection electrode in monolithic sensors, both for bulk or epitaxial layer technologies [13, 14], as well as for Silicon on Insulator (SOI) technologies [15]

Low electric field sensor regions

Transient three-dimensional TCAD simulations

Pixel modifications

Pixel size

Sensor reverse bias

Summary